1. Field of the Invention
The present disclosure pertains to a low-consumption voltage regulator.
2. Description of the Related Art
Linear voltage regulators of the ULDO (Ultra Low Drop Out) type are known in the state of the art. ULDO regulators are widely used in portable applications, in motorcars and in medical applications. These applications are fed by batteries that require low stand-by currents to increase the lifespan and the efficiency of the battery.
The efficiency of the regulator clashes with its time specifications. Indeed, a higher feeding current determines a faster response of the regulator. This is due to the charging and discharging of parasitic capacitances connected to the driving terminal of the power transistors of the voltage regulator, with parasitic capacitances on the order of hundreds of picofarads. Therefore, if the output load is varied, considerable current peaks are required by the voltage regulator to charge and discharge the parasitic capacitances in the shortest possible time.
A voltage regulator of the ULDO type is described in the article “A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator” by Gabriel A. Rincon-Mora and Philip E. Allen, IEEE Journal of Solid State Circuit, vol. 33, No. 1, January 1998, and is shown in FIG. 1. The regulator in FIG. 1 is a class A error operational amplifier 1 having on the inverting input a reference voltage Vref and on the non-inverting input a fraction Vr of the regulator output voltage Vout with Vr=(R2/(R1+R2))*Vout. The amplifier is fed by a voltage Vin and its output is connected to a buffer stage 2 comprising an NPN common collector bipolar transistor Q1, a MOS transistor mirror M1-M2 connected between the emitter terminal of transistor Q1 and the drain terminal of a transistor M3 having the source terminal connected to voltage Vin and the gate terminal connected to the emitter terminal of transistor Q1 and to the gate terminal of power transistor Mp. The latter has the source terminal connected to voltage Vin and the drain terminal connected to the series of resistors R1 and R2 connected to ground. A polarization current generator Ibias is connected to the gate and drain terminals of transistor M2.
Buffer stage 2 allows to release the parasitic capacitance Cpar of the power transistor Mp from the output terminal of error amplifier 1 but introduces in the regulator loop gain a third pole which complicates the compensation of the regulator. By recovering a fraction Iboost of output current Iload a certain stability of the system is guaranteed; in this case, indeed, the pole formed by the introduction of buffer stage 2 may be preferably shifted over the cut-off frequency of the open-loop gain of the regulator. Benefits may also be obtained in the response time of the regulator by appropriately dimensioning current Iboost.
However, if the current in load Iload has a low value, the corresponding fraction of current Iboost becomes very small and practically null; in such a case, no benefit derives in terms of response in time.